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| author | Dave.Wen <dave.wen@sifive.com> | 2019-04-25 01:50:46 -0700 |
|---|---|---|
| committer | Dave.Wen <dave.wen@sifive.com> | 2019-04-25 01:50:46 -0700 |
| commit | f6ecc5bb21a690ef3c3a5c3b95259307ff5da938 (patch) | |
| tree | 930871fd50c26ffe9c144171bda2a4ef9a7077d6 /riscv/processor.h | |
| parent | 4265438d34183efeccb377cbe5a2a444c7507827 (diff) | |
| download | spike-f6ecc5bb21a690ef3c3a5c3b95259307ff5da938.zip spike-f6ecc5bb21a690ef3c3a5c3b95259307ff5da938.tar.gz spike-f6ecc5bb21a690ef3c3a5c3b95259307ff5da938.tar.bz2 | |
rvv: fix vsmulv[vx]
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index eae4581..ae15cc7 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -200,9 +200,7 @@ struct vectorUnit_t { reg_t get_slen() { return SLEN; } VRM get_vround_mode() { - uint32_t rm = BITS(vxrm, 0, 2); - assert( rm < VRM::INVALID_RM ); - return (VRM)rm; + return (VRM)vxrm; } }; |