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| author | Tim Newsome <tim@sifive.com> | 2019-07-16 13:29:45 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-07-22 02:11:03 -0700 |
| commit | cf482745a833428fef10bbbf8376c9c092727458 (patch) | |
| tree | b717fbe8a007b9f844e1c3c06486d19b696dacb6 /riscv/processor.h | |
| parent | 98b4b07cb428eb0be1c96e857ab52b68a30c9f2e (diff) | |
| download | spike-cf482745a833428fef10bbbf8376c9c092727458.zip spike-cf482745a833428fef10bbbf8376c9c092727458.tar.gz spike-cf482745a833428fef10bbbf8376c9c092727458.tar.bz2 | |
Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)
* Don't corrupt s0 when abstract CSR write fails.
* Support abstract FPR access then mstatus.FS=0
Discussion on the spec list leans towards this being a requirement.
Certainly users want their debugger to be able to access all registers
regardless of target state.
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 9698145..b6d6416 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -243,7 +243,7 @@ struct state_t reg_t scause; reg_t dpc; - reg_t dscratch; + reg_t dscratch0, dscratch1; dcsr_t dcsr; reg_t tselect; mcontrol_t mcontrol[num_triggers]; |