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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-04-15 21:04:20 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-04-15 21:04:20 -0700 |
| commit | b97e4fb1a7ab774ca8f340a9d7eb30a4455b387f (patch) | |
| tree | b2e894e49c6e663edf57a402f71cd7affd45f27b /riscv/processor.h | |
| parent | 6db96b82734ff74f616aea6cbbb80b3a787223c3 (diff) | |
| download | spike-b97e4fb1a7ab774ca8f340a9d7eb30a4455b387f.zip spike-b97e4fb1a7ab774ca8f340a9d7eb30a4455b387f.tar.gz spike-b97e4fb1a7ab774ca8f340a9d7eb30a4455b387f.tar.bz2 | |
Revert "Revert "rvv: restore reg_reference keeping""
revert wrong revert
This reverts commit ffda9507ae644cc7700608b12d3facd2849e4cad.
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index b290c18..e47fc09 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -166,6 +166,9 @@ struct vectorUnit_t { T& elt(reg_t vReg, reg_t n){ // this still needs to be adjusted for SLEN != VLEN assert(vsew!=0); + reg_t elts_per_reg = (VLEN >> 3) / (sizeof(T)); + vReg += n / elts_per_reg; + n = n % elts_per_reg; reg_referenced[vReg] = 1; #if 0 if (((vReg & reg_mask) != vReg) || (n >= vlmax)){ |