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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-04-15 07:47:19 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-04-15 07:47:19 -0700 |
| commit | 9ce7f63c81535f79b1ab6fa2472393901d801581 (patch) | |
| tree | 7d7e3b84b930e1db8bb822d098d1a631e2a82ac6 /riscv/processor.h | |
| parent | 9192c166011f9ccbc85b72959c36bf6fa978e993 (diff) | |
| download | spike-9ce7f63c81535f79b1ab6fa2472393901d801581.zip spike-9ce7f63c81535f79b1ab6fa2472393901d801581.tar.gz spike-9ce7f63c81535f79b1ab6fa2472393901d801581.tar.bz2 | |
Revert "rvv: restore reg_reference keeping"
This reverts commit 085310bf0a14ca66cffeb73c4fa37fea2be2fe6c.
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index e47fc09..b290c18 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -166,9 +166,6 @@ struct vectorUnit_t { T& elt(reg_t vReg, reg_t n){ // this still needs to be adjusted for SLEN != VLEN assert(vsew!=0); - reg_t elts_per_reg = (VLEN >> 3) / (sizeof(T)); - vReg += n / elts_per_reg; - n = n % elts_per_reg; reg_referenced[vReg] = 1; #if 0 if (((vReg & reg_mask) != vReg) || (n >= vlmax)){ |