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author | Dave <dave.wen@sifive.com> | 2019-04-20 16:02:24 -0700 |
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committer | Dave <dave.wen@sifive.com> | 2019-04-20 16:06:12 -0700 |
commit | 7e162161e5702aadef2c5d27085be6929febb3c6 (patch) | |
tree | 03edd66ce6c4109d03ef6bc999cadf69561ede0f /riscv/processor.h | |
parent | 5256af4170a1a9e176fca59e489a0a9bd7333926 (diff) | |
download | spike-7e162161e5702aadef2c5d27085be6929febb3c6.zip spike-7e162161e5702aadef2c5d27085be6929febb3c6.tar.gz spike-7e162161e5702aadef2c5d27085be6929febb3c6.tar.bz2 |
improve the vectorUint_t
1. for vill, we need to know the XLEN from VU. So we put a pointer to
processor in vectorUnit_t
2. add vill
3. fitting the naming convention for setVL
Diffstat (limited to 'riscv/processor.h')
-rw-r--r-- | riscv/processor.h | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index e47fc09..99582ce 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -152,14 +152,17 @@ struct type_sew_t<64> }; struct vectorUnit_t { + processor_t* p; void *reg_file; - char reg_referenced[NVPR]; + char reg_referenced[NVPR]; int setvl_count; - reg_t reg_mask, vstart, vl, vlmax, vsew; - reg_t vxrm, vxsat, vlmul, vmlen; - reg_t ELEN, VLEN, SLEN, LMUL, vtype; + reg_t reg_mask, vlmax, vmlen; + reg_t vstart, vxrm, vxsat, vl, vtype; + reg_t vediv, vsew, vlmul; + reg_t ELEN, VLEN, SLEN, LMUL; + bool vill; - reg_t setVL(uint64_t regId, reg_t reqVL, reg_t newType); + reg_t set_vl(uint64_t regId, reg_t reqVL, reg_t newType); // vector element for varies SEW template<class T> |