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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-10-15 21:26:13 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-10-15 21:26:13 -0700 |
| commit | 3742f48eb3186c5a36d4e29bef57ab73e9d5edb7 (patch) | |
| tree | cb0918fe29e97d0fbb1f59059f3a47d7c789e7cf /riscv/processor.h | |
| parent | 8d6a4bc0f0fe7c834eaf58b0e455cea9355c2cd0 (diff) | |
| download | spike-3742f48eb3186c5a36d4e29bef57ab73e9d5edb7.zip spike-3742f48eb3186c5a36d4e29bef57ab73e9d5edb7.tar.gz spike-3742f48eb3186c5a36d4e29bef57ab73e9d5edb7.tar.bz2 | |
rvv: add new rs1 = zero feature to vsetvl
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 1591645..ef0319f 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -196,7 +196,7 @@ class vectorUnit_t { reg_file = 0; } - reg_t set_vl(uint64_t regId, reg_t reqVL, reg_t newType); + reg_t set_vl(int regId, reg_t reqVL, reg_t newType); reg_t get_vlen() { return VLEN; } reg_t get_elen() { return ELEN; } |