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authorDave.Wen <dave.wen@sifive.com>2019-04-07 15:03:01 +0800
committerDave.Wen <dave.wen@sifive.com>2019-04-07 15:03:01 +0800
commit22aa983c65c3e89f5f51d3978da21cda77993595 (patch)
tree0c90f61b97b1cf736e6434f8558dd6cec0bb8a73 /riscv/processor.h
parent2bb0360c3088721a1f51e85df3045362bd213ed5 (diff)
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rvv: add unsigned sew type
Diffstat (limited to 'riscv/processor.h')
-rw-r--r--riscv/processor.h28
1 files changed, 28 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h
index 538f873..3700ab5 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -97,6 +97,34 @@ enum VRM{
};
template<uint64_t N>
+struct type_usew_t;
+
+template<>
+struct type_usew_t<8>
+{
+ using type=uint8_t;
+};
+
+template<>
+struct type_usew_t<16>
+{
+ using type=uint16_t;
+};
+
+template<>
+struct type_usew_t<32>
+{
+ using type=uint32_t;
+};
+
+template<>
+struct type_usew_t<64>
+{
+ using type=uint64_t;
+};
+
+
+template<uint64_t N>
struct type_sew_t;
template<>