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| author | Tim Newsome <tim@sifive.com> | 2022-03-15 10:58:04 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-03-30 10:41:45 -0700 |
| commit | fd315a0ddebdfbee71edbfb60680cdbf43bc4c38 (patch) | |
| tree | ba4fe724efe3fc8da17b1012b825a2d77f0ba91f /riscv/processor.h | |
| parent | 16ed520e8d35a0eaa56b708aa540400312acdc09 (diff) | |
| download | spike-fd315a0ddebdfbee71edbfb60680cdbf43bc4c38.zip spike-fd315a0ddebdfbee71edbfb60680cdbf43bc4c38.tar.gz spike-fd315a0ddebdfbee71edbfb60680cdbf43bc4c38.tar.bz2 | |
Move tdata2 into mcontrol_t
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index ba352fc..baa2934 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -352,7 +352,7 @@ public: value &= 0xffffffff; } - auto tdata2 = state.tdata2->read(i); + auto tdata2 = TM.triggers[i]->tdata2; switch (TM.triggers[i]->match) { case triggers::mcontrol_t::MATCH_EQUAL: if (value != tdata2) |