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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-10 22:55:07 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-10 23:05:58 +0800 |
| commit | ce34edb0eecec520d6d2cfec5bda57ca90a69f14 (patch) | |
| tree | f5f5da62f53bced28e38349a1b41983bb916dcfa /riscv/processor.h | |
| parent | 2aaa89c0cf8fe0f45d284c0847f11d175eb82e03 (diff) | |
| download | spike-ce34edb0eecec520d6d2cfec5bda57ca90a69f14.zip spike-ce34edb0eecec520d6d2cfec5bda57ca90a69f14.tar.gz spike-ce34edb0eecec520d6d2cfec5bda57ca90a69f14.tar.bz2 | |
Add space between if/while/switch and '('
Add space between ')' and '{'
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 88ddf70..073b25b 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -406,7 +406,7 @@ public: // vector element for varies SEW template<class T> - T& elt(reg_t vReg, reg_t n, bool is_write = false){ + T& elt(reg_t vReg, reg_t n, bool is_write = false) { assert(vsew != 0); assert((VLEN >> 3)/sizeof(T) > 0); reg_t elts_per_reg = (VLEN >> 3) / (sizeof(T)); @@ -453,7 +453,7 @@ public: vstart_alu(false) { } - ~vectorUnit_t(){ + ~vectorUnit_t() { free(reg_file); reg_file = 0; } |