Split out MINSTRET and MCYCLE

Before this change, the MCYCLE CSR was just a proxy for MINSTRET.
Similarly, CYCLE was a proxy for INSTRET. This models a machine where
every instruction takes exactly one cycle to execute.

That's not quite precise enough if you want to do cosimulation: there,
you're going to want to MCYCLE to actually match the behaviour of your
processor (because you need reads from the relevant CSRs to give the
expected result).

This commit splits the two CSRs, leaving the other proxy relationships
unchanged. The code in processor_t::step() which bumps MINSTRET now
bumps MCYCLE by the same amount, maintaining the previous behaviour.

Of course, now a cosimulation environment can update the value of
MCYCLE to fix things up for multi-cycle instructions after they run.

1 files changed, 1 insertions, 0 deletions

diff --git a/riscv/processor.h b/riscv/processor.h
index 986431d..f58ec4b 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -177,6 +177,7 @@ struct state_t
   csr_t_p mtvec;
   csr_t_p mcause;
   wide_counter_csr_t_p minstret;
+  wide_counter_csr_t_p mcycle;
   mie_csr_t_p mie;
   mip_csr_t_p mip;
   csr_t_p medeleg;