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authorTim Newsome <tim@sifive.com>2022-03-15 10:13:21 -0700
committerTim Newsome <tim@sifive.com>2022-03-30 10:41:44 -0700
commitc0445333d880c13bb7a1b8af2bf74ed1d957a0af (patch)
treea7973dab649593f35ed30de4bfd83aa4b43bd588 /riscv/processor.h
parent9e9f56166d4205aabfcef841951c292272e87801 (diff)
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mcontrol_match_t -> mcontrol_t::match_t
Made mcontrol_t a class as well.
Diffstat (limited to 'riscv/processor.h')
-rw-r--r--riscv/processor.h12
1 files changed, 6 insertions, 6 deletions
diff --git a/riscv/processor.h b/riscv/processor.h
index d12ca93..2136571 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -355,33 +355,33 @@ public:
auto tdata2 = state.tdata2->read(i);
switch (state.mcontrol[i].match) {
- case triggers::MATCH_EQUAL:
+ case triggers::mcontrol_t::MATCH_EQUAL:
if (value != tdata2)
continue;
break;
- case triggers::MATCH_NAPOT:
+ case triggers::mcontrol_t::MATCH_NAPOT:
{
reg_t mask = ~((1 << (cto(tdata2)+1)) - 1);
if ((value & mask) != (tdata2 & mask))
continue;
}
break;
- case triggers::MATCH_GE:
+ case triggers::mcontrol_t::MATCH_GE:
if (value < tdata2)
continue;
break;
- case triggers::MATCH_LT:
+ case triggers::mcontrol_t::MATCH_LT:
if (value >= tdata2)
continue;
break;
- case triggers::MATCH_MASK_LOW:
+ case triggers::mcontrol_t::MATCH_MASK_LOW:
{
reg_t mask = tdata2 >> (xlen/2);
if ((value & mask) != (tdata2 & mask))
continue;
}
break;
- case triggers::MATCH_MASK_HIGH:
+ case triggers::mcontrol_t::MATCH_MASK_HIGH:
{
reg_t mask = tdata2 >> (xlen/2);
if (((value >> (xlen/2)) & mask) != (tdata2 & mask))