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author | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-22 10:27:14 -0700 |
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committer | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-26 17:17:52 -0700 |
commit | ab8e2fe519e81cf1cfd1dbecbf3ec172cd9db666 (patch) | |
tree | 9bd2e51f730381617129ace8af294bb80ccb401e /riscv/processor.h | |
parent | d39d439b44f726262b7f047219f76f6ecbb7b277 (diff) | |
download | spike-ab8e2fe519e81cf1cfd1dbecbf3ec172cd9db666.zip spike-ab8e2fe519e81cf1cfd1dbecbf3ec172cd9db666.tar.gz spike-ab8e2fe519e81cf1cfd1dbecbf3ec172cd9db666.tar.bz2 |
Convert tselect to csr_t
Diffstat (limited to 'riscv/processor.h')
-rw-r--r-- | riscv/processor.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index d1737c5..7ffca95 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -204,7 +204,7 @@ struct state_t reg_t dpc; reg_t dscratch0, dscratch1; dcsr_t dcsr; - reg_t tselect; + csr_t_p tselect; mcontrol_t mcontrol[num_triggers]; reg_t tdata2[num_triggers]; bool debug_mode; |