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| author | Tsukasa #01 (a4lg) <research_trasio@irq.a4lg.com> | 2021-12-08 11:28:44 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-12-07 18:28:44 -0800 |
| commit | a68c7b12e6b9e9b9abd7ad1cee05c4a8432719ec (patch) | |
| tree | 5ce0295f0e44d09ed9c87accc75bd6f4228a0197 /riscv/processor.h | |
| parent | 9b3b305e42d9427618b08c33b5dfe1b5180b9f43 (diff) | |
| download | spike-a68c7b12e6b9e9b9abd7ad1cee05c4a8432719ec.zip spike-a68c7b12e6b9e9b9abd7ad1cee05c4a8432719ec.tar.gz spike-a68c7b12e6b9e9b9abd7ad1cee05c4a8432719ec.tar.bz2 | |
Add 'Zfhmin' extension (#880)
Zfhmin is a subset of Zfh (half-precision IEEE 754 binary16 floating
point) extension, consisting only of data transfer and conversion
instructions.
This commit adds `EXT_ZFHMIN` to `isa_extension_t`, permits "zfhmin"
as a multi-letter extension and adjusts feature gate for
data transfer / conversion instructions.
* FLH / FSH
* FMV.X.H / FMV.H.X
* FCVT.S.H / FCVT.H.S
* FCVT.D.H / FCVT.H.D (if 'D' extension is also present)
* FCVT.Q.H / FCVT.H.Q (if 'Q' extension is also present)
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index a7c75f6..c32f624 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -230,6 +230,7 @@ typedef enum { typedef enum { // 65('A') ~ 90('Z') is reserved for standard isa in misa EXT_ZFH, + EXT_ZFHMIN, EXT_ZBA, EXT_ZBB, EXT_ZBC, |