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authorTim Newsome <tim@sifive.com>2022-03-15 08:14:50 -0700
committerTim Newsome <tim@sifive.com>2022-03-30 10:38:53 -0700
commita2a2587426e57f6207d5389620e9109bc0f82e6b (patch)
tree94ac06e2e8797bf0a8ef3b4c08175450f37acd83 /riscv/processor.h
parent273fa05167c873e2cc92862ddbb52b10806f439a (diff)
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trigger_operation_t -> triggers::operation_t
Diffstat (limited to 'riscv/processor.h')
-rw-r--r--riscv/processor.h9
1 files changed, 5 insertions, 4 deletions
diff --git a/riscv/processor.h b/riscv/processor.h
index 7d05346..1b5c818 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -15,6 +15,7 @@
#include "entropy_source.h"
#include "csrs.h"
#include "isa_parser.h"
+#include "triggers.h"
class processor_t;
class mmu_t;
@@ -355,7 +356,7 @@ public:
} halt_request;
// Return the index of a trigger that matched, or -1.
- inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)
+ inline int trigger_match(triggers::operation_t operation, reg_t address, reg_t data)
{
if (state.debug_mode)
return -1;
@@ -368,9 +369,9 @@ public:
continue;
}
- if ((operation == OPERATION_EXECUTE && !state.mcontrol[i].execute) ||
- (operation == OPERATION_STORE && !state.mcontrol[i].store) ||
- (operation == OPERATION_LOAD && !state.mcontrol[i].load) ||
+ if ((operation == triggers::OPERATION_EXECUTE && !state.mcontrol[i].execute) ||
+ (operation == triggers::OPERATION_STORE && !state.mcontrol[i].store) ||
+ (operation == triggers::OPERATION_LOAD && !state.mcontrol[i].load) ||
(state.prv == PRV_M && !state.mcontrol[i].m) ||
(state.prv == PRV_S && !state.mcontrol[i].s) ||
(state.prv == PRV_U && !state.mcontrol[i].u)) {