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| author | soberl@nvidia.com <soberl@nvidia.com> | 2022-05-03 19:38:07 -0700 |
|---|---|---|
| committer | soberl@nvidia.com <soberl@nvidia.com> | 2022-05-04 18:26:24 -0700 |
| commit | 84a98f6f718cd482710238042eac3d2b855c6768 (patch) | |
| tree | 31e3e1e5cb9a7459e3678b75df953390cdfb025d /riscv/processor.h | |
| parent | 1df65613df9970dc7f5c2f3d1bf343dbb0497828 (diff) | |
| download | spike-84a98f6f718cd482710238042eac3d2b855c6768.zip spike-84a98f6f718cd482710238042eac3d2b855c6768.tar.gz spike-84a98f6f718cd482710238042eac3d2b855c6768.tar.bz2 | |
Implement the new csr mseccfg for ePMP as dummy
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 8797ab1..96fdc54 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -179,6 +179,8 @@ struct state_t tdata2_csr_t_p tdata2; bool debug_mode; + mseccfg_csr_t_p mseccfg; + static const int max_pmp = 16; pmpaddr_csr_t_p pmpaddr[max_pmp]; |