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| author | Andrew Waterman <andrew@sifive.com> | 2022-01-06 15:41:12 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-01-06 15:42:38 -0800 |
| commit | 5b7cdbe1cf75112bd2a472b7490b15fa7078d798 (patch) | |
| tree | 18792b68df01868a8349de1b7c529f34c0784b43 /riscv/processor.h | |
| parent | 336a5813fd3f72d5081344466bcbd3275227dae7 (diff) | |
| download | spike-5b7cdbe1cf75112bd2a472b7490b15fa7078d798.zip spike-5b7cdbe1cf75112bd2a472b7490b15fa7078d798.tar.gz spike-5b7cdbe1cf75112bd2a472b7490b15fa7078d798.tar.bz2 | |
DRY in selecting instruction functions
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index c32f624..2d14bb3 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -29,6 +29,8 @@ struct insn_desc_t insn_bits_t mask; insn_func_t rv32; insn_func_t rv64; + + insn_func_t func(int xlen) { return xlen == 64 ? rv64 : rv32; } }; // regnum, data |