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| author | Andrew Waterman <andrew@sifive.com> | 2022-03-15 23:01:45 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-03-16 13:47:27 -0700 |
| commit | 5698007158cc5f0d9b39c7a5446ddb7cbc935b2b (patch) | |
| tree | 28092599053350f3106667aa4f3eeccc1455db6f /riscv/processor.h | |
| parent | a522178805264c9bfb8ebd68db33fabfa9ddd3ae (diff) | |
| download | spike-5698007158cc5f0d9b39c7a5446ddb7cbc935b2b.zip spike-5698007158cc5f0d9b39c7a5446ddb7cbc935b2b.tar.gz spike-5698007158cc5f0d9b39c7a5446ddb7cbc935b2b.tar.bz2 | |
Inline most implicit accesses to fflags/frm
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 3e9a743..7f64857 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -217,8 +217,8 @@ struct state_t static const int max_pmp = 16; pmpaddr_csr_t_p pmpaddr[max_pmp]; - csr_t_p fflags; - csr_t_p frm; + float_csr_t_p fflags; + float_csr_t_p frm; csr_t_p menvcfg; csr_t_p senvcfg; |