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| author | i2h2 <110197402+i2h2@users.noreply.github.com> | 2022-08-03 16:01:57 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-08-03 15:01:57 -0700 |
| commit | 5672c4a41ad7a9af011d385962c175a5a6012fd9 (patch) | |
| tree | 2b2268331e4bb8011f3578492d846568113ca990 /riscv/processor.h | |
| parent | 14cb6b2a6244e3a1511c4c169676a6e2bd6785ed (diff) | |
| download | spike-5672c4a41ad7a9af011d385962c175a5a6012fd9.zip spike-5672c4a41ad7a9af011d385962c175a5a6012fd9.tar.gz spike-5672c4a41ad7a9af011d385962c175a5a6012fd9.tar.bz2 | |
Add Sstc support. (#1057)
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index b415402..88ddf70 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -193,6 +193,10 @@ struct state_t csr_t_p htimedelta; time_counter_csr_t_p time; + csr_t_p time_proxy; + + csr_t_p stimecmp; + csr_t_p vstimecmp; bool serialized; // whether timer CSRs are in a well-defined state |