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authorChih-Min Chao <chihmin.chao@sifive.com>2022-02-20 22:28:09 -0800
committerChih-Min Chao <chihmin.chao@sifive.com>2022-02-23 19:13:20 -0800
commit53a3002e8cdbf94016d36c6071945bd663e826d5 (patch)
treec5957ee2569442ab014b7c734c688de3007bcf49 /riscv/processor.h
parentb3e8d381a61f62c7d43f5dfa22ffc94d55f25223 (diff)
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perf: refine csr accessibility checking
1. support zicntr and zihpm performance extensions zicntr defines the unprivileged cycle/time/instret zihpm defines the unprivileged hpmcounter3-31 2. the accessibility are controlled only by mcounteren/scounteren/hcounteren for access in different privilege modes Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/processor.h')
-rw-r--r--riscv/processor.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h
index f58ec4b..9ee3e6c 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -280,6 +280,8 @@ typedef enum {
EXT_ZHINXMIN,
EXT_ZICBOM,
EXT_ZICBOZ,
+ EXT_ZICNTR,
+ EXT_ZIHPM,
EXT_XZBP,
EXT_XZBS,
EXT_XZBE,