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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-08 20:30:02 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-21 08:50:26 +0800 |
| commit | 3ff1b5f1c6c6e13777be1c677abc2340f3dabd1a (patch) | |
| tree | b5c4481531b8da56e2aa4ef5473c148ef0b9f177 /riscv/processor.h | |
| parent | 28ee0c4d6a1ed221f1a05ba48f54023ac7d455cc (diff) | |
| download | spike-3ff1b5f1c6c6e13777be1c677abc2340f3dabd1a.zip spike-3ff1b5f1c6c6e13777be1c677abc2340f3dabd1a.tar.gz spike-3ff1b5f1c6c6e13777be1c677abc2340f3dabd1a.tar.bz2 | |
add support for time/timeh/htimedelta/htimedeltah csrs
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 347ae16..b415402 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -191,6 +191,9 @@ struct state_t csr_t_p sstateen[4]; csr_t_p hstateen[4]; + csr_t_p htimedelta; + time_counter_csr_t_p time; + bool serialized; // whether timer CSRs are in a well-defined state // When true, execute a single instruction and then enter debug mode. This |