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| author | Andrew Waterman <andrew@sifive.com> | 2022-09-20 14:35:28 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-20 14:35:28 -0700 |
| commit | 326fa00f587c43f76d94acbeaed83ffba2e07d3b (patch) | |
| tree | 1328145c71687481ab58a9a935cceb956c87d7b9 /riscv/processor.h | |
| parent | ccc9791807b59d848e7c8983cea49a16fb4a2912 (diff) | |
| parent | 32e199cce48a7b837e026bf072b8fd1a8f9c62f6 (diff) | |
| download | spike-326fa00f587c43f76d94acbeaed83ffba2e07d3b.zip spike-326fa00f587c43f76d94acbeaed83ffba2e07d3b.tar.gz spike-326fa00f587c43f76d94acbeaed83ffba2e07d3b.tar.bz2 | |
Merge pull request #1036 from plctlab/plct-sscofpmf-dev
add support for sscofpmf extension v0.5.2
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 3937211..7fc4be7 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -145,6 +145,7 @@ struct state_t csr_t_p medeleg; csr_t_p mideleg; csr_t_p mcounteren; + csr_t_p mevent[29]; csr_t_p scounteren; csr_t_p sepc; csr_t_p stval; |