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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-06 10:45:04 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-09 08:56:00 +0800 |
| commit | 2bf74857f0f7f3a63e029d7c7ecaf3d4523a846e (patch) | |
| tree | ad5f41de37fa05c7097f0788cca850e2b932cf01 /riscv/processor.h | |
| parent | 9b66f89b8102f032f721fe332819325508aa3b95 (diff) | |
| download | spike-2bf74857f0f7f3a63e029d7c7ecaf3d4523a846e.zip spike-2bf74857f0f7f3a63e029d7c7ecaf3d4523a846e.tar.gz spike-2bf74857f0f7f3a63e029d7c7ecaf3d4523a846e.tar.bz2 | |
add support for csrs of smstateen extensions
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 0c6a6b2..727c404 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -186,6 +186,10 @@ struct state_t csr_t_p senvcfg; csr_t_p henvcfg; + csr_t_p mstateen[4]; + csr_t_p sstateen[4]; + csr_t_p hstateen[4]; + bool serialized; // whether timer CSRs are in a well-defined state // When true, execute a single instruction and then enter debug mode. This |