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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-01 16:09:02 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-07 08:31:11 +0800 |
| commit | 2aedbdd01911a42565cd6d154f82fa00a66410cd (patch) | |
| tree | 441ee02f16e3e3faa9fcf88b826899c391b4e13b /riscv/processor.h | |
| parent | ac466a21df442c59962589ba296c702631e041b5 (diff) | |
| download | spike-2aedbdd01911a42565cd6d154f82fa00a66410cd.zip spike-2aedbdd01911a42565cd6d154f82fa00a66410cd.tar.gz spike-2aedbdd01911a42565cd6d154f82fa00a66410cd.tar.bz2 | |
remove multi blank lines
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index ec1b400..0c6a6b2 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -118,7 +118,6 @@ struct type_sew_t<64> using type=int64_t; }; - // architectural state of a RISC-V hart struct state_t { |