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| author | liweiwei <liweiwei@iscas.ac.cn> | 2021-12-27 11:04:04 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-01-29 17:22:40 +0800 |
| commit | 14e54ebb9359d6dd1e41b54ca94dc034d3bfd577 (patch) | |
| tree | e98e6d037ce96bee332b2482a63819f6d530b720 /riscv/processor.h | |
| parent | 42cbf10dc1f6c6ce0a9591a53be2555f75da6c87 (diff) | |
| download | spike-14e54ebb9359d6dd1e41b54ca94dc034d3bfd577.zip spike-14e54ebb9359d6dd1e41b54ca94dc034d3bfd577.tar.gz spike-14e54ebb9359d6dd1e41b54ca94dc034d3bfd577.tar.bz2 | |
add isa string, csr support for cmo extensions
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 35f8afc..9ef1bce 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -218,6 +218,11 @@ struct state_t csr_t_p fflags; csr_t_p frm; + + csr_t_p menvcfg; + csr_t_p senvcfg; + csr_t_p henvcfg; + bool serialized; // whether timer CSRs are in a well-defined state // When true, execute a single instruction and then enter debug mode. This @@ -269,6 +274,8 @@ typedef enum { EXT_SVPBMT, EXT_SVINVAL, EXT_XBITMANIP, + EXT_ZICBOM, + EXT_ZICBOZ, } isa_extension_t; typedef enum { |