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| author | Marcus Comstedt <marcus@mc.pp.se> | 2019-08-18 16:03:43 +0200 |
|---|---|---|
| committer | Marcus Comstedt <marcus@mc.pp.se> | 2019-10-28 09:23:32 +0100 |
| commit | f437e6a4e9983be0583ee1bf34512f80f3cc0162 (patch) | |
| tree | f3ac0efc442019566f31aa5ba26c78915e80a0b6 /riscv/processor.h | |
| parent | 5652b9dd6298c7b61fe80bc2a508bbd3c9e5c5ef (diff) | |
| download | spike-f437e6a4e9983be0583ee1bf34512f80f3cc0162.zip spike-f437e6a4e9983be0583ee1bf34512f80f3cc0162.tar.gz spike-f437e6a4e9983be0583ee1bf34512f80f3cc0162.tar.bz2 | |
Implement support for big-endian hosts
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 2b5003b..68e6249 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -177,6 +177,11 @@ class vectorUnit_t { reg_t elts_per_reg = (VLEN >> 3) / (sizeof(T)); vReg += n / elts_per_reg; n = n % elts_per_reg; +#ifdef WORDS_BIGENDIAN + // "V" spec 0.7.1 requires lower indices to map to lower significant + // bits when changing SEW, thus we need to index from the end on BE. + n ^= elts_per_reg - 1; +#endif reg_referenced[vReg] = 1; T *regStart = (T*)((char*)reg_file + vReg * (VLEN >> 3)); |