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| author | Andrew Waterman <andrew@sifive.com> | 2018-09-20 17:00:46 -0700 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-09-25 03:55:11 -0700 |
| commit | 55ef17645dd61a8e59a826118f23e7077ac9ab26 (patch) | |
| tree | 361d10bf476a3d7f3780f096c7eeeb67c1b1b36b /riscv/processor.h | |
| parent | 0b8700bb6196f201c3519c944aa7f9ea881a55b8 (diff) | |
| download | spike-55ef17645dd61a8e59a826118f23e7077ac9ab26.zip spike-55ef17645dd61a8e59a826118f23e7077ac9ab26.tar.gz spike-55ef17645dd61a8e59a826118f23e7077ac9ab26.tar.bz2 | |
Add PMP support
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index fd90ce3..de0be78 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -123,6 +123,10 @@ struct state_t mcontrol_t mcontrol[num_triggers]; reg_t tdata2[num_triggers]; + static const int n_pmp = 16; + uint8_t pmpcfg[n_pmp]; + reg_t pmpaddr[n_pmp]; + uint32_t fflags; uint32_t frm; bool serialized; // whether timer CSRs are in a well-defined state |