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| author | Andrew Waterman <andrew@sifive.com> | 2019-07-11 15:11:27 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-11 15:11:27 -0700 |
| commit | cbb979ddfb5201287c5d60d335bf1f12649e0a04 (patch) | |
| tree | e577e39e5d7a327bb8681993e689af5616c340bf /riscv/processor.cc | |
| parent | 364e9c641257738b3f1ba9f23d9fe0a0ccafce06 (diff) | |
| download | spike-cbb979ddfb5201287c5d60d335bf1f12649e0a04.zip spike-cbb979ddfb5201287c5d60d335bf1f12649e0a04.tar.gz spike-cbb979ddfb5201287c5d60d335bf1f12649e0a04.tar.bz2 | |
Fix support for 32-bit hosts (but no V extension in that case!)
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index d182f7a..ca49b41 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -127,7 +127,11 @@ void processor_t::parse_isa_string(const char* str) lowercase += std::tolower(*r); const char* p = lowercase.c_str(); - const char* all_subsets = "imafdqcv"; + const char* all_subsets = "imafdqc" +#ifdef __SIZEOF_INT128__ + "v" +#endif + ""; max_xlen = 64; state.misa = reg_t(2) << 62; |