diff options
| author | Andrew Waterman <andrew@sifive.com> | 2017-11-01 18:57:02 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-11-01 18:57:02 -0700 |
| commit | 8b389440b7aff4cf7f81dd17babc649abec810b3 (patch) | |
| tree | 1bad3cdb1b673ccf9d9204cda7975c70ec275feb /riscv/processor.cc | |
| parent | 3b1e9ab7522b3b20cde6bd8d9f2b28222463cf1b (diff) | |
| download | spike-8b389440b7aff4cf7f81dd17babc649abec810b3.zip spike-8b389440b7aff4cf7f81dd17babc649abec810b3.tar.gz spike-8b389440b7aff4cf7f81dd17babc649abec810b3.tar.bz2 | |
Don't permit delegation of interrupts that M-mode should handle
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index ae02165..203394b 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -360,10 +360,9 @@ void processor_t::set_csr(int which, reg_t val) state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints); break; case CSR_MEDELEG: { - reg_t mask = 0; -#define DECLARE_CAUSE(name, value) mask |= 1ULL << (value); -#include "encoding.h" -#undef DECLARE_CAUSE + reg_t mask = CAUSE_MISALIGNED_FETCH | CAUSE_BREAKPOINT + | CAUSE_USER_ECALL | CAUSE_FETCH_PAGE_FAULT + | CAUSE_LOAD_PAGE_FAULT | CAUSE_STORE_PAGE_FAULT; state.medeleg = (state.medeleg & ~mask) | (val & mask); break; } |