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| author | Dave.Wen <dave.wen@sifive.com> | 2020-05-07 05:59:07 -0700 |
|---|---|---|
| committer | Dave.Wen <dave.wen@sifive.com> | 2020-05-07 05:59:07 -0700 |
| commit | 3baafbe3559fb62b8a4d3f13288593035e4502d3 (patch) | |
| tree | 42f99317b2b11c2fe1e3a8f79de8a1852e4d4cdb /riscv/processor.cc | |
| parent | f471e0edac1be60e92b96518cb653fa5f173af07 (diff) | |
| download | spike-3baafbe3559fb62b8a4d3f13288593035e4502d3.zip spike-3baafbe3559fb62b8a4d3f13288593035e4502d3.tar.gz spike-3baafbe3559fb62b8a4d3f13288593035e4502d3.tar.bz2 | |
rvv: add eew and lmul for vle/vse/vleff
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 926bd37..827ea1d 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -374,10 +374,14 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT vtype = newType; vsew = 1 << (BITS(newType, 4, 2) + 3); vlmul = 1 << BITS(newType, 1, 0); - vediv = 1 << BITS(newType, 6, 5); - vlmax = VLEN/vsew * vlmul; - vmlen = vsew / vlmul; - reg_mask = (NVPR-1) & ~(vlmul-1); + vemul = vlmul; + veew = vsew; + fractional_lmul = BITS(newType, 5, 5); + vta = BITS(newType, 6, 6); + vma = BITS(newType, 7, 7); + vediv = 1 << BITS(newType, 9, 8); + vlmax = fractional_lmul? (VLEN/vsew)/vlmul : VLEN/vsew * vlmul; + vmlen = fractional_lmul? 1 : vsew / vlmul; vill = vsew > ELEN || vediv != 1 || (newType >> 7) != 0; if (vill) { |