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| author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-05-06 15:49:34 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-05-06 15:49:34 -0700 |
| commit | ef2e75f0bdeb5eea92a62f293041f202f8ee6f46 (patch) | |
| tree | 3f9dff18f021d2d327d49e07d0d0a47334bf4141 /riscv/mmu.h | |
| parent | 46f2fb1d9e33b4cf98c2cc15c2a2da14f0e3580d (diff) | |
| download | spike-ef2e75f0bdeb5eea92a62f293041f202f8ee6f46.zip spike-ef2e75f0bdeb5eea92a62f293041f202f8ee6f46.tar.gz spike-ef2e75f0bdeb5eea92a62f293041f202f8ee6f46.tar.bz2 | |
[sim] fixed building sim without cache simulators
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index f8ee597..1277856 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -23,7 +23,7 @@ public: do { if(dcsim) (dcsim)->tick(addr, size, st); \ if(dtlbsim) (dtlbsim)->tick(addr, sizeof(reg_t), false); } while(0) #else - # define dcsim_tick(dcsim, addr, size) + # define dcsim_tick(dcsim, dtlbsim, addr, size, st) #endif #define load_func(type) \ |