[xcc,sim] eliminated vectored traps

now, the evec register holds the address that all traps vector to,
and the cause register is set with the trap number.

1 files changed, 2 insertions, 2 deletions

diff --git a/riscv/mmu.h b/riscv/mmu.h
index 9bfbeac..1b8a422 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -50,9 +50,9 @@ private:
   {
     if(addr & (size-1))
     {
+      badvaddr = addr;
       if(fetch)
         throw trap_instruction_address_misaligned;
-      badvaddr = addr;
       throw trap_data_address_misaligned;
     }
   }
@@ -61,9 +61,9 @@ private:
   {
     if(addr >= memsz || addr + size > memsz)
     {
+      badvaddr = addr;
       if(fetch)
         throw trap_instruction_access_fault;
-      badvaddr = addr;
       throw store ? trap_store_access_fault : trap_load_access_fault;
     }
   }