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| author | Andrew Waterman <andrew@sifive.com> | 2016-11-13 16:10:30 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2016-11-13 16:10:45 -0800 |
| commit | 679d5f5e927a0a59bbaaab33955ded79e860cded (patch) | |
| tree | da664f501c8eaa4a791e0caf986e6409a64f74b5 /riscv/mmu.h | |
| parent | 3a7393db14e1d5daf7ba4b019e1234d35dab9a10 (diff) | |
| download | spike-679d5f5e927a0a59bbaaab33955ded79e860cded.zip spike-679d5f5e927a0a59bbaaab33955ded79e860cded.tar.gz spike-679d5f5e927a0a59bbaaab33955ded79e860cded.tar.bz2 | |
Fix 32-bit host portability bug
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 105908e..34bcf99 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -202,7 +202,7 @@ private: static const reg_t TLB_ENTRIES = 256; // If a TLB tag has TLB_CHECK_TRIGGERS set, then the MMU must check for a // trigger match before completing an access. - static const reg_t TLB_CHECK_TRIGGERS = 1L<<63; + static const reg_t TLB_CHECK_TRIGGERS = reg_t(1) << 63; char* tlb_data[TLB_ENTRIES]; reg_t tlb_insn_tag[TLB_ENTRIES]; reg_t tlb_load_tag[TLB_ENTRIES]; |