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| author | sven <zhongcy93@163.com> | 2021-05-25 18:05:04 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-05-25 03:05:04 -0700 |
| commit | e2691f0a53e083b7495b6aa50634ac22d464369b (patch) | |
| tree | 09b177f48ea75528345668e8dea8e6d8720cc7ba /riscv/mmu.h | |
| parent | 46300119843e117dee006008d07129f0e83fd23b (diff) | |
| download | spike-e2691f0a53e083b7495b6aa50634ac22d464369b.zip spike-e2691f0a53e083b7495b6aa50634ac22d464369b.tar.gz spike-e2691f0a53e083b7495b6aa50634ac22d464369b.tar.bz2 | |
Add alignment check for lr instruction (#713)
Co-authored-by: zhongcy <zhongcy93@gmail.com>
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index f009679..af4bcd1 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -253,8 +253,11 @@ public: load_reservation_address = (reg_t)-1; } - inline void acquire_load_reservation(reg_t vaddr) + inline void acquire_load_reservation(reg_t vaddr, size_t size) { + if (vaddr & (size-1)) + load_reserved_address_misaligned(vaddr); + reg_t paddr = translate(vaddr, 1, LOAD, 0); if (auto host_addr = sim->addr_to_mem(paddr)) load_reservation_address = refill_tlb(vaddr, paddr, host_addr, LOAD).target_offset + vaddr; |