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authorliweiwei <liweiwei@iscas.ac.cn>2021-12-27 11:34:02 +0800
committerWeiwei Li <liweiwei@iscas.ac.cn>2022-01-30 11:33:03 +0800
commite205ca655c12df1ae0f6f3105bc8a671b049f161 (patch)
tree5994a35a1995f8dd55aefdf5db2ae00bb61f44f5 /riscv/mmu.h
parent456913b2c97d55993103594991a7ac73453465f8 (diff)
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add instructions function for cmo
prefetch.* are hints and share the encoding of ORI with rd = 0. so it can share the implementation of ORI and execute as no-ops
Diffstat (limited to 'riscv/mmu.h')
-rw-r--r--riscv/mmu.h50
1 files changed, 36 insertions, 14 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h
index af11078..017b483 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -184,27 +184,30 @@ public:
} \
}
+ // AMO/Zicbom faults should be reported as store faults
+ #define convert_load_traps_to_store_traps(BODY) \
+ try { \
+ BODY \
+ } catch (trap_load_address_misaligned& t) { \
+ /* Misaligned fault will not be triggered by Zicbom */ \
+ throw trap_store_address_misaligned(t.has_gva(), t.get_tval(), t.get_tval2(), t.get_tinst()); \
+ } catch (trap_load_page_fault& t) { \
+ throw trap_store_page_fault(t.has_gva(), t.get_tval(), t.get_tval2(), t.get_tinst()); \
+ } catch (trap_load_access_fault& t) { \
+ throw trap_store_access_fault(t.has_gva(), t.get_tval(), t.get_tval2(), t.get_tinst()); \
+ } catch (trap_load_guest_page_fault& t) { \
+ throw trap_store_guest_page_fault(t.get_tval(), t.get_tval2(), t.get_tinst()); \
+ }
+
// template for functions that perform an atomic memory operation
#define amo_func(type) \
template<typename op> \
type##_t amo_##type(reg_t addr, op f) { \
- try { \
+ convert_load_traps_to_store_traps({ \
auto lhs = load_##type(addr, true); \
store_##type(addr, f(lhs)); \
return lhs; \
- } catch (trap_load_address_misaligned& t) { \
- /* AMO faults should be reported as store faults */ \
- throw trap_store_address_misaligned(t.has_gva(), t.get_tval(), t.get_tval2(), t.get_tinst()); \
- } catch (trap_load_page_fault& t) { \
- /* AMO faults should be reported as store faults */ \
- throw trap_store_page_fault(t.has_gva(), t.get_tval(), t.get_tval2(), t.get_tinst()); \
- } catch (trap_load_access_fault& t) { \
- /* AMO faults should be reported as store faults */ \
- throw trap_store_access_fault(t.has_gva(), t.get_tval(), t.get_tval2(), t.get_tinst()); \
- } catch (trap_load_guest_page_fault& t) { \
- /* AMO faults should be reported as store faults */ \
- throw trap_store_guest_page_fault(t.get_tval(), t.get_tval2(), t.get_tinst()); \
- } \
+ }) \
}
void store_float128(reg_t addr, float128_t val)
@@ -242,6 +245,25 @@ public:
amo_func(uint32)
amo_func(uint64)
+ void cbo_zero(reg_t addr) {
+ auto base = addr & ~(blocksz - 1);
+ for (size_t offset = 0; offset < blocksz; offset += 1)
+ store_uint8(base + offset, 0);
+ }
+
+ void clean_inval(reg_t addr, bool clean, bool inval) {
+ convert_load_traps_to_store_traps({
+ reg_t paddr = addr & ~(blocksz - 1);
+ paddr = translate(paddr, blocksz, LOAD, 0);
+ if (auto host_addr = sim->addr_to_mem(paddr)) {
+ if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
+ tracer.clean_invalidate(paddr, blocksz, clean, inval);
+ } else {
+ throw trap_store_access_fault((proc) ? proc->state.v : false, addr, 0, 0);
+ }
+ })
+ }
+
inline void yield_load_reservation()
{
load_reservation_address = (reg_t)-1;