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| author | Andrew Waterman <andrew@sifive.com> | 2022-09-22 17:34:33 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-04 15:40:01 -0700 |
| commit | ce69fb5db97ecf240336b7826dd9dddeb32e5dca (patch) | |
| tree | f78647d0eafa9abc414f5ded2a3663c7506cfd9c /riscv/mmu.h | |
| parent | a51e44ed228e48fc1dbf24ec7dc23cbd61a7874a (diff) | |
| download | spike-ce69fb5db97ecf240336b7826dd9dddeb32e5dca.zip spike-ce69fb5db97ecf240336b7826dd9dddeb32e5dca.tar.gz spike-ce69fb5db97ecf240336b7826dd9dddeb32e5dca.tar.bz2 | |
Suppress most unused variable warnings
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index ca8b792..1cd614b 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -52,7 +52,7 @@ public: #define RISCV_XLATE_VIRT (1U << 0) #define RISCV_XLATE_VIRT_HLVX (1U << 1) - inline reg_t misaligned_load(reg_t addr, size_t size, uint32_t xlate_flags) + inline reg_t misaligned_load(reg_t addr, size_t UNUSED size, uint32_t xlate_flags) { #ifdef RISCV_ENABLE_MISALIGNED reg_t res = 0; @@ -72,7 +72,7 @@ public: #endif } - inline void misaligned_store(reg_t addr, reg_t data, size_t size, uint32_t xlate_flags, bool actually_store=true) + inline void misaligned_store(reg_t addr, reg_t UNUSED data, size_t UNUSED size, uint32_t xlate_flags, bool UNUSED actually_store=true) { #ifdef RISCV_ENABLE_MISALIGNED for (size_t i = 0; i < size; i++) { |