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| author | Andrew Waterman <andrew@sifive.com> | 2022-09-22 18:01:06 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-04 15:40:01 -0700 |
| commit | c20c4a2331a6a2f2cf9e170a9b387024ef543b47 (patch) | |
| tree | 3cc105f0bc390b0b23bb7e2dc3218217ec3e7ea7 /riscv/mmu.h | |
| parent | 09369aa5f8a5de7868b75ef15bc0ebf4e9e3e101 (diff) | |
| download | spike-c20c4a2331a6a2f2cf9e170a9b387024ef543b47.zip spike-c20c4a2331a6a2f2cf9e170a9b387024ef543b47.tar.gz spike-c20c4a2331a6a2f2cf9e170a9b387024ef543b47.tar.bz2 | |
Suppress most unused-variable warnings
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 1cd614b..4d52618 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -91,7 +91,7 @@ public: } #ifndef RISCV_ENABLE_COMMITLOG -# define READ_MEM(addr, size) ({}) +# define READ_MEM(addr, size) ((void)(addr), (void)(size)) #else # define READ_MEM(addr, size) \ proc->state.log_mem_read.push_back(std::make_tuple(addr, 0, size)); @@ -154,7 +154,7 @@ public: load_func(int64, guest_load, RISCV_XLATE_VIRT) #ifndef RISCV_ENABLE_COMMITLOG -# define WRITE_MEM(addr, value, size) ({}) +# define WRITE_MEM(addr, value, size) ((void)(addr), (void)(value), (void)(size)) #else # define WRITE_MEM(addr, val, size) \ proc->state.log_mem_write.push_back(std::make_tuple(addr, val, size)); @@ -265,7 +265,7 @@ public: convert_load_traps_to_store_traps({ const reg_t vaddr = addr & ~(blocksz - 1); const reg_t paddr = translate(vaddr, blocksz, LOAD, 0); - if (auto host_addr = sim->addr_to_mem(paddr)) { + if (sim->addr_to_mem(paddr)) { if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD)) tracer.clean_invalidate(paddr, blocksz, clean, inval); } else { |