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authorAndrew Waterman <waterman@cs.berkeley.edu>2016-04-29 13:48:56 -0700
committerAndrew Waterman <waterman@cs.berkeley.edu>2016-04-29 13:48:56 -0700
commitb593e6df7afc0d356fa0ca0a8c2c8d05f1b87bd8 (patch)
tree69fa3354e48322b2166b01bfa6a209b775381a99 /riscv/mmu.h
parent9220fdfe955379af4c6cff00e7925a650b2180a5 (diff)
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Move much closer to new platform-M memory map
Reset vector is at 0x1000; below that is reserved for debug Memory is at 0x80000000
Diffstat (limited to 'riscv/mmu.h')
-rw-r--r--riscv/mmu.h16
1 files changed, 6 insertions, 10 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h
index b9948c5..b6aa2ca 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -7,6 +7,7 @@
#include "trap.h"
#include "common.h"
#include "config.h"
+#include "sim.h"
#include "processor.h"
#include "memtracer.h"
#include <stdlib.h>
@@ -33,7 +34,7 @@ struct icache_entry_t {
class mmu_t
{
public:
- mmu_t(char* _mem, size_t _memsz);
+ mmu_t(sim_t* sim, processor_t* proc);
~mmu_t();
// template for functions that load an aligned value from memory
@@ -93,10 +94,7 @@ public:
int length = insn_length(insn);
if (likely(length == 4)) {
- if (likely(addr % PGSIZE < PGSIZE-2))
- insn |= (insn_bits_t)*(const int16_t*)(iaddr + 1) << 16;
- else
- insn |= (insn_bits_t)*(const int16_t*)translate_insn_addr(addr + 2) << 16;
+ insn |= (insn_bits_t)*(const int16_t*)translate_insn_addr(addr + 2) << 16;
} else if (length == 2) {
insn = (int16_t)insn;
} else if (length == 6) {
@@ -113,7 +111,7 @@ public:
entry->tag = addr;
entry->data = fetch;
- reg_t paddr = (const char*)iaddr - mem;
+ reg_t paddr = sim->mem_to_addr((char*)iaddr);
if (tracer.interested_in_range(paddr, paddr + 1, FETCH)) {
entry->tag = -1;
tracer.trace(paddr, length, FETCH);
@@ -134,18 +132,16 @@ public:
return access_icache(addr)->data;
}
- void set_processor(processor_t* p) { proc = p; flush_tlb(); }
-
void flush_tlb();
void flush_icache();
void register_memtracer(memtracer_t*);
private:
- char* mem;
- size_t memsz;
+ sim_t* sim;
processor_t* proc;
memtracer_list_t tracer;
+ uint16_t fetch_temp;
// implement an instruction cache for simulator performance
icache_entry_t icache[ICACHE_ENTRIES];