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| author | Scott Johnson <scott.johnson@arilinc.com> | 2022-07-15 18:08:00 -0700 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2022-07-15 18:16:38 -0700 |
| commit | a2697ac775dac31e0aabf0223171b1e2f8a7fcde (patch) | |
| tree | 9d5d69e6e160b9656dfbf663b7b976dbeccbfe84 /riscv/mmu.h | |
| parent | 031681b2f3bfa120769d9ead1ca866ca1be163b4 (diff) | |
| download | spike-a2697ac775dac31e0aabf0223171b1e2f8a7fcde.zip spike-a2697ac775dac31e0aabf0223171b1e2f8a7fcde.tar.gz spike-a2697ac775dac31e0aabf0223171b1e2f8a7fcde.tar.bz2 | |
Split up misaligned store into several steps
Since the last step is about to get much more complex
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 6d8072b..f652bf8 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -71,8 +71,11 @@ public: inline void misaligned_store(reg_t addr, reg_t data, size_t size, uint32_t xlate_flags, bool actually_store=true) { #ifdef RISCV_ENABLE_MISALIGNED - for (size_t i = 0; i < size; i++) - store_uint8(addr + (target_big_endian? size-1-i : i), data >> (i * 8), actually_store); + for (size_t i = 0; i < size; i++) { + const reg_t byteaddr = addr + (target_big_endian? size-1-i : i); + const reg_t bytedata = data >> (i * 8); + store_uint8(byteaddr, bytedata, actually_store); + } #else bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags); throw trap_store_address_misaligned(gva, addr, 0, 0); |