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| author | Andrew Waterman <andrew@sifive.com> | 2021-07-21 18:51:41 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-07-21 18:51:41 -0700 |
| commit | 9cfc3e7fef7b29f6b53879d7c91c35459d9b493d (patch) | |
| tree | 4b0ea1a2eef02a95d583715bdfe96158b9b48952 /riscv/mmu.h | |
| parent | 4deb3750337d93663333ca5f643004120b7d9c7d (diff) | |
| download | spike-9cfc3e7fef7b29f6b53879d7c91c35459d9b493d.zip spike-9cfc3e7fef7b29f6b53879d7c91c35459d9b493d.tar.gz spike-9cfc3e7fef7b29f6b53879d7c91c35459d9b493d.tar.bz2 | |
Fix hypervisor MXR and SUM
When V=1, vsstatus.MXR applies to the first stage of translation,
and mstatus.MXR applies to both.
mstatus.SUM doesn't apply when V=1, but vsstatus.SUM does.
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 3e44002..a43b17e 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -414,10 +414,10 @@ private: const char* fill_from_mmio(reg_t vaddr, reg_t paddr); // perform a stage2 translation for a given guest address - reg_t s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_type, bool virt, bool mxr, bool hlvx); + reg_t s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_type, bool virt, bool hlvx); // perform a page table walk for a given VA; set referenced/dirty bits - reg_t walk(reg_t addr, access_type type, reg_t prv, bool virt, bool mxr, bool hlvx); + reg_t walk(reg_t addr, access_type type, reg_t prv, bool virt, bool hlvx); // handle uncommon cases: TLB misses, page faults, MMIO tlb_entry_t fetch_slow_path(reg_t addr); |