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| author | Tim Newsome <tim@sifive.com> | 2016-05-04 09:45:56 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:12 -0700 |
| commit | 850e745dcf300cd5369d006b31e17ebfb417eab4 (patch) | |
| tree | 3607d8bdf46a750c66bb0ae582bd4c233cf96ac0 /riscv/mmu.h | |
| parent | ee96c255f12477b1762426ceb7bbd83370c899cd (diff) | |
| download | spike-850e745dcf300cd5369d006b31e17ebfb417eab4.zip spike-850e745dcf300cd5369d006b31e17ebfb417eab4.tar.gz spike-850e745dcf300cd5369d006b31e17ebfb417eab4.tar.bz2 | |
Use fence.i in Debug ROM.
This replaces a hack that just disabled all of the icache.
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 8fe3043..a87b6af 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -117,7 +117,6 @@ public: entry->tag = -1; tracer.trace(paddr, length, FETCH); } - entry->tag = -1; // TODO: this is hack to work around Debug RAM code being cached return entry; } |