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| author | Andrew Waterman <andrew@sifive.com> | 2022-10-06 17:40:41 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-06 19:30:40 -0700 |
| commit | 7b8114f707a7b2de9fd2d393b9d019180de83025 (patch) | |
| tree | dc4c83a2ab0e7050758214025c15991f9e78a5eb /riscv/mmu.h | |
| parent | fd50768df9ec4d9f80c6a37d89734d9e27443f6b (diff) | |
| download | spike-7b8114f707a7b2de9fd2d393b9d019180de83025.zip spike-7b8114f707a7b2de9fd2d393b9d019180de83025.tar.gz spike-7b8114f707a7b2de9fd2d393b9d019180de83025.tar.bz2 | |
Don't use reexecution as the means to implement trigger-after
The scheme was based on the notion that memory accesses are idempotent
up until the point the trigger would've been hit, which isn't true in
the case of side-effecting loads and data-value triggers.
Instead, check the trigger on the next instruction fetch. To keep the
perf overhead minimal, perform this check on the I$ refill path, and
ensure that path is taken by flushing the I$.
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 8eeea31..01e74ef 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -247,6 +247,9 @@ public: inline icache_entry_t* refill_icache(reg_t addr, icache_entry_t* entry) { + if (matched_trigger) + throw *matched_trigger; + auto tlb_entry = translate_insn_addr(addr); insn_bits_t insn = from_le(*(uint16_t*)(tlb_entry.host_offset + addr)); int length = insn_length(insn); |