diff options
| author | sven <zhongcy93@163.com> | 2021-06-13 08:59:13 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-06-12 17:59:13 -0700 |
| commit | 3e2c6136df04117b997cad6bfd93b8b19264f08f (patch) | |
| tree | 985a3e4c9518ad03f0539d423500d8afe998b9c6 /riscv/mmu.h | |
| parent | 1908fc380c24ef0989063e8029eaa14913c187dd (diff) | |
| download | spike-3e2c6136df04117b997cad6bfd93b8b19264f08f.zip spike-3e2c6136df04117b997cad6bfd93b8b19264f08f.tar.gz spike-3e2c6136df04117b997cad6bfd93b8b19264f08f.tar.bz2 | |
Revert the redundant check for lr instruction (#728)
Co-authored-by: zhongchengyong <zhongcy93@gmail.com>
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index af4bcd1..f009679 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -253,11 +253,8 @@ public: load_reservation_address = (reg_t)-1; } - inline void acquire_load_reservation(reg_t vaddr, size_t size) + inline void acquire_load_reservation(reg_t vaddr) { - if (vaddr & (size-1)) - load_reserved_address_misaligned(vaddr); - reg_t paddr = translate(vaddr, 1, LOAD, 0); if (auto host_addr = sim->addr_to_mem(paddr)) load_reservation_address = refill_tlb(vaddr, paddr, host_addr, LOAD).target_offset + vaddr; |