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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-07-26 18:12:36 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-07-26 18:12:36 -0700 |
| commit | b357c97b249cdb13cc08f0893d73994662b5be8d (patch) | |
| tree | 4945a8f9088735c025b02d11abfd21bf83260d7f /riscv/mmu.h | |
| parent | bda232b0117adbc949b87ffb71fda34e51c891bc (diff) | |
| download | spike-b357c97b249cdb13cc08f0893d73994662b5be8d.zip spike-b357c97b249cdb13cc08f0893d73994662b5be8d.tar.gz spike-b357c97b249cdb13cc08f0893d73994662b5be8d.tar.bz2 | |
Remove more vector stuff
Diffstat (limited to 'riscv/mmu.h')
| -rw-r--r-- | riscv/mmu.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 49a5f0b..64b11d3 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -104,9 +104,6 @@ public: // load instruction from memory at aligned address. inline insn_fetch_t load_insn(reg_t addr) { -#ifdef RISCV_ENABLE_RVC -# error TODO: Make MMU instruction cache support 2-byte alignment -#endif reg_t idx = (addr/sizeof(insn_t::itype)) % ICACHE_ENTRIES; if (unlikely(icache_tag[idx] != addr)) { |