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author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-03-29 18:35:25 -0700 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-03-29 18:35:25 -0700 |
commit | b189b9b128ce619f9423009062a85ccb17b32db9 (patch) | |
tree | 519ee4bd22ea039d28690294461a02b2ce66635f /riscv/mmu.h | |
parent | 983a062e287ebe0d69c17448e67da6223cf48080 (diff) | |
download | spike-b189b9b128ce619f9423009062a85ccb17b32db9.zip spike-b189b9b128ce619f9423009062a85ccb17b32db9.tar.gz spike-b189b9b128ce619f9423009062a85ccb17b32db9.tar.bz2 |
add load-reserved/store-conditional instructions
Diffstat (limited to 'riscv/mmu.h')
-rw-r--r-- | riscv/mmu.h | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 43a3ec9..a5d150f 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -53,6 +53,10 @@ public: } \ reg_t paddr = translate(addr, sizeof(type##_t), false, false); \ return *(type##_t*)(mem + paddr); \ + } \ + type##_t load_reserved_##type(reg_t addr) { \ + load_reservation = addr; \ + return load_##type(addr); \ } // load value from memory at aligned address; zero extend to register width @@ -77,6 +81,12 @@ public: } \ reg_t paddr = translate(addr, sizeof(type##_t), true, false); \ *(type##_t*)(mem + paddr) = val; \ + } \ + reg_t store_conditional_##type(reg_t addr, type##_t val) { \ + if (addr == load_reservation) { \ + store_##type(addr, val); \ + return 0; \ + } else return 1; \ } // store value to memory at aligned address @@ -148,8 +158,8 @@ public: // get/set the page table base register reg_t get_ptbr() { return ptbr; } void set_ptbr(reg_t addr) { ptbr = addr & ~(PGSIZE-1); flush_tlb(); } - // keep the MMU in sync with processor mode - void set_sr(uint32_t _sr) { sr = _sr; } + void yield_load_reservation() { load_reservation = -1; } + void set_sr(uint32_t sr); // keep the MMU in sync with the processor mode // flush the TLB and instruction cache void flush_tlb(); @@ -160,6 +170,7 @@ public: private: char* mem; size_t memsz; + reg_t load_reservation; reg_t badvaddr; reg_t ptbr; uint32_t sr; |