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authorAndrew Waterman <aswaterman@gmail.com>2015-01-02 15:09:04 -0800
committerAndrew Waterman <aswaterman@gmail.com>2015-01-02 15:09:04 -0800
commit3fd738af16ef977f1aa507e2525bb4c16fff9026 (patch)
tree4b2ba07a5b3fd928fe17d330c262296547f48f00 /riscv/mmu.h
parente104cd11f504c2de3d1fdfa2ce9193f8f878d15c (diff)
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Reduce dependences on auto-generated code
In particular, precompiled headers ideally won't depend on any.
Diffstat (limited to 'riscv/mmu.h')
-rw-r--r--riscv/mmu.h7
1 files changed, 4 insertions, 3 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h
index 778e5fa..08d41be 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -4,7 +4,6 @@
#define _RISCV_MMU_H
#include "decode.h"
-#include "icache.h"
#include "trap.h"
#include "common.h"
#include "config.h"
@@ -74,10 +73,12 @@ public:
store_func(uint32)
store_func(uint64)
+ static const reg_t ICACHE_ENTRIES = 1024;
+
inline size_t icache_index(reg_t addr)
{
// for instruction sizes != 4, this hash still works but is suboptimal
- return (addr / 4) % ICACHE_SIZE;
+ return (addr / 4) % ICACHE_ENTRIES;
}
// load instruction from memory at aligned address.
@@ -140,7 +141,7 @@ private:
memtracer_list_t tracer;
// implement an instruction cache for simulator performance
- icache_entry_t icache[ICACHE_SIZE];
+ icache_entry_t icache[ICACHE_ENTRIES];
// implement a TLB for simulator performance
static const reg_t TLB_ENTRIES = 256;