diff options
| author | Andrew Waterman <andrew@sifive.com> | 2019-07-12 11:55:01 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-12 11:55:01 -0700 |
| commit | cc6e8787edd5112f3f4476b56022fffc98b2f3be (patch) | |
| tree | 6dea8df996c56b7d971bbd10ad312fe84ac48835 /riscv/mmu.cc | |
| parent | ee3ef2b189227ee84b33ef69e5c7e9897fea6ba4 (diff) | |
| download | spike-cc6e8787edd5112f3f4476b56022fffc98b2f3be.zip spike-cc6e8787edd5112f3f4476b56022fffc98b2f3be.tar.gz spike-cc6e8787edd5112f3f4476b56022fffc98b2f3be.tar.bz2 | |
Add debug_mode state bit, rather than overloading dcsr.cause
In the previous scheme, debug-mode software could exit debug mode by
zeroing the dcsr.cause field. While benign, that behavior is out of
spec.
Diffstat (limited to 'riscv/mmu.cc')
| -rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 506b99f..a0e500b 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -51,7 +51,7 @@ reg_t mmu_t::translate(reg_t addr, reg_t len, access_type type) reg_t mode = proc->state.prv; if (type != FETCH) { - if (!proc->state.dcsr.cause && get_field(proc->state.mstatus, MSTATUS_MPRV)) + if (!proc->state.debug_mode && get_field(proc->state.mstatus, MSTATUS_MPRV)) mode = get_field(proc->state.mstatus, MSTATUS_MPP); } |