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| author | Tim Newsome <tim@sifive.com> | 2016-05-01 12:05:48 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
| commit | 990c6c48098e83584edf5282d119187abae04a4d (patch) | |
| tree | d2ba581b281dce0c329822f98cc7c21faf868323 /riscv/mmu.cc | |
| parent | 57ff1b6595e485b8b002238ddbd10483bbd62fb3 (diff) | |
| download | spike-990c6c48098e83584edf5282d119187abae04a4d.zip spike-990c6c48098e83584edf5282d119187abae04a4d.tar.gz spike-990c6c48098e83584edf5282d119187abae04a4d.tar.bz2 | |
Have Debug memory kind of working again.
Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
Diffstat (limited to 'riscv/mmu.cc')
| -rw-r--r-- | riscv/mmu.cc | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 514547c..dee41a9 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -51,28 +51,6 @@ reg_t mmu_t::translate(reg_t addr, access_type type) return walk(addr, type, mode > PRV_U, pum) | (addr & (PGSIZE-1)); } -const char* mmu_t::fill_from_mmio(reg_t vaddr, reg_t paddr) -{ - reg_t rv_start = paddr & PGMASK; - char* spike_start = proc->sim->mmio_page(rv_start); - - if (!spike_start) - return NULL; - - // TODO: refactor with refill_tlb() - reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES; - reg_t expected_tag = vaddr >> PGSHIFT; - - if (tlb_load_tag[idx] != expected_tag) tlb_load_tag[idx] = -1; - if (tlb_store_tag[idx] != expected_tag) tlb_store_tag[idx] = -1; - if (tlb_insn_tag[idx] != expected_tag) tlb_insn_tag[idx] = -1; - - tlb_insn_tag[idx] = expected_tag; - tlb_data[idx] = spike_start - DEBUG_START; - - return spike_start + (paddr & ~PGMASK); -} - const uint16_t* mmu_t::fetch_slow_path(reg_t vaddr) { reg_t paddr = translate(vaddr, FETCH); |