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author | Scott Johnson <scott.johnson@arilinc.com> | 2021-03-04 16:28:39 -0800 |
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committer | Andrew Waterman <aswaterman@gmail.com> | 2021-09-08 07:59:02 -0700 |
commit | f4db821afbfdd7b2c5f00fd239c084f6036b7094 (patch) | |
tree | d85632757baa8f98e5cb37e8efceacb2954136b5 /riscv/mmu.cc | |
parent | a9720fb0f89047aeff661f86eeaa3fc941efd8a8 (diff) | |
download | spike-f4db821afbfdd7b2c5f00fd239c084f6036b7094.zip spike-f4db821afbfdd7b2c5f00fd239c084f6036b7094.tar.gz spike-f4db821afbfdd7b2c5f00fd239c084f6036b7094.tar.bz2 |
Convert mstatus into csr_t family
Step 3 of plan described in csrs.h.
Diffstat (limited to 'riscv/mmu.cc')
-rw-r--r-- | riscv/mmu.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index c214884..a9c056c 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -57,9 +57,9 @@ reg_t mmu_t::translate(reg_t addr, reg_t len, access_type type, uint32_t xlate_f bool hlvx = xlate_flags & RISCV_XLATE_VIRT_HLVX; reg_t mode = proc->state.prv; if (type != FETCH) { - if (!proc->state.debug_mode && get_field(proc->state.mstatus, MSTATUS_MPRV)) { - mode = get_field(proc->state.mstatus, MSTATUS_MPP); - if (get_field(proc->state.mstatus, MSTATUS_MPV) && mode != PRV_M) + if (!proc->state.debug_mode && get_field(proc->state.mstatus->read(), MSTATUS_MPRV)) { + mode = get_field(proc->state.mstatus->read(), MSTATUS_MPP); + if (get_field(proc->state.mstatus->read(), MSTATUS_MPV) && mode != PRV_M) virt = true; } if (xlate_flags & RISCV_XLATE_VIRT) { @@ -190,7 +190,7 @@ tlb_entry_t mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, char* host_addr, access_ tlb_entry_t entry = {host_addr - vaddr, paddr - vaddr}; - if (proc && get_field(proc->state.mstatus, MSTATUS_MPRV)) + if (proc && get_field(proc->state.mstatus->read(), MSTATUS_MPRV)) return entry; if ((tlb_load_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag) |