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| author | Scott Johnson <scott.johnson@arilinc.com> | 2021-03-04 21:12:41 -0800 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2021-09-08 07:59:02 -0700 |
| commit | dc7dfc7015dfa983e62f8ad0aa1d0f4accc7e500 (patch) | |
| tree | 11510630b41319e22264c3cd1e9a6b506caa6c38 /riscv/mmu.cc | |
| parent | 36f62570b64d66cea6d7772c34abcd944a004adf (diff) | |
| download | spike-dc7dfc7015dfa983e62f8ad0aa1d0f4accc7e500.zip spike-dc7dfc7015dfa983e62f8ad0aa1d0f4accc7e500.tar.gz spike-dc7dfc7015dfa983e62f8ad0aa1d0f4accc7e500.tar.bz2 | |
Convert sstatus to virtualized_csr_t
Step 5 of plan in csrs.h.
This changes the commitlog to properly report when the architectural
`vsstatus` register is written, e.g. by `csrw sstatus` in VS-mode.
Diffstat (limited to 'riscv/mmu.cc')
| -rw-r--r-- | riscv/mmu.cc | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index a9c056c..7f2858c 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -267,8 +267,7 @@ reg_t mmu_t::s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_ty if (vm.levels == 0) return gpa; - reg_t arch_sstatus = proc->state.v ? proc->state.vsstatus->read() : proc->state.sstatus->read(); - bool mxr = arch_sstatus & MSTATUS_MXR; + bool mxr = proc->state.sstatus->readvirt(false) & MSTATUS_MXR; reg_t base = vm.ptbase; for (int i = vm.levels - 1; i >= 0; i--) { @@ -347,9 +346,9 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode, bool virt, bool hlvx return s2xlate(addr, addr & ((reg_t(2) << (proc->xlen-1))-1), type, type, virt, hlvx) & ~page_mask; // zero-extend from xlen bool s_mode = mode == PRV_S; - reg_t arch_vsstatus = proc->state.v ? proc->state.sstatus->read() : proc->state.vsstatus->read(); - reg_t arch_sstatus = proc->state.v ? proc->state.vsstatus->read() : proc->state.sstatus->read(); - bool sum = (virt ? arch_vsstatus : arch_sstatus) & MSTATUS_SUM; + bool sum = proc->state.sstatus->readvirt(virt) & MSTATUS_SUM; + reg_t arch_vsstatus = proc->state.sstatus->readvirt(true); + reg_t arch_sstatus = proc->state.sstatus->readvirt(false); bool mxr = (arch_sstatus | (virt ? arch_vsstatus : 0)) & MSTATUS_MXR; // verify bits xlen-1:va_bits-1 are all equal |