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authorRyan Buchner <ryan.buchner@arilinc.com>2022-04-12 13:54:32 -0700
committerRyan Buchner <ryan.buchner@arilinc.com>2022-04-13 09:47:38 -0700
commit38c1fcda44a410da1ec55577e91ee9910a8c189a (patch)
tree4ab2f9727f137a47f328b72aebd820d96103cd8f /riscv/mmu.cc
parent147ed1bc807360c4c90784f975c24693cdd291d4 (diff)
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Adjust indentation in store_slow_path and store_func
Didn't want to make change in previous commit to isolate the change.
Diffstat (limited to 'riscv/mmu.cc')
-rw-r--r--riscv/mmu.cc18
1 files changed, 9 insertions, 9 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 40dccf0..1ef81cf 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -173,15 +173,15 @@ void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes, uint32_
}
if (actually_store) {
- if (auto host_addr = sim->addr_to_mem(paddr)) {
- memcpy(host_addr, bytes, len);
- if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
- tracer.trace(paddr, len, STORE);
- else if (xlate_flags == 0)
- refill_tlb(addr, paddr, host_addr, STORE);
- } else if (!mmio_store(paddr, len, bytes)) {
- throw trap_store_access_fault((proc) ? proc->state.v : false, addr, 0, 0);
- }
+ if (auto host_addr = sim->addr_to_mem(paddr)) {
+ memcpy(host_addr, bytes, len);
+ if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
+ tracer.trace(paddr, len, STORE);
+ else if (xlate_flags == 0)
+ refill_tlb(addr, paddr, host_addr, STORE);
+ } else if (!mmio_store(paddr, len, bytes)) {
+ throw trap_store_access_fault((proc) ? proc->state.v : false, addr, 0, 0);
+ }
}
}